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| author | Loic GUEGAN <loic.guegan@yahoo.fr> | 2018-09-01 16:49:12 +0200 |
|---|---|---|
| committer | Loic GUEGAN <loic.guegan@yahoo.fr> | 2018-09-01 16:49:12 +0200 |
| commit | d58349763a312add267dbcaf53d0b9602b177d33 (patch) | |
| tree | d9fb59898059b8e0e726f7e637eefcfa4697d9e1 /micsim.py | |
| parent | 6ac0692116f34750f24460d1d4b09cb72f51d422 (diff) | |
Debug MBR register
Diffstat (limited to 'micsim.py')
| -rwxr-xr-x | micsim.py | 1 |
1 files changed, 0 insertions, 1 deletions
@@ -13,4 +13,3 @@ c["RAM"]=RAM # Add ram to components mic=Microprogram(c) # Create micro program mic.run() # Run the micro program mic.dump() # Dump ram - |
