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| author | Loic GUEGAN <loic.guegan@yahoo.fr> | 2018-09-01 19:09:48 +0200 |
|---|---|---|
| committer | Loic GUEGAN <loic.guegan@yahoo.fr> | 2018-09-01 19:09:48 +0200 |
| commit | 4a9d274fd70ce2531311f19debcf22f0faa1f9b2 (patch) | |
| tree | 195405f55705f7f7266398e2edb346d89ad44703 /components/microprogram.py | |
| parent | 94377da94d085948557b25a73ce143d51611aa7f (diff) | |
Add little endianess, debug memory addressing
Diffstat (limited to 'components/microprogram.py')
| -rw-r--r-- | components/microprogram.py | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/components/microprogram.py b/components/microprogram.py index 8ae9703..869a2ae 100644 --- a/components/microprogram.py +++ b/components/microprogram.py @@ -1,9 +1,6 @@ from components.ijvm import ijvm -# TODO: Switch MAR as 32bits address (multiply its value by for) -# then same for SP and LV - class Microprogram: def __init__(self,components): @@ -164,7 +161,7 @@ class Microprogram: print("-------------- RAM --------------") self.c["RAM"].dump() print("------------- Stack -------------") - self.c["RAM"].dumpRange(self.c["LV"],self.c["SP"]) + self.c["RAM"].dumpRange(self.c["LV"]*4,self.c["SP"]*4,4) # Convert address to 32bits value print("----------- Registers -----------") for key,value in self.c.items(): if key!="RAM": |