From 4a9d274fd70ce2531311f19debcf22f0faa1f9b2 Mon Sep 17 00:00:00 2001 From: Loic GUEGAN Date: Sat, 1 Sep 2018 19:09:48 +0200 Subject: Add little endianess, debug memory addressing --- components/microprogram.py | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'components/microprogram.py') diff --git a/components/microprogram.py b/components/microprogram.py index 8ae9703..869a2ae 100644 --- a/components/microprogram.py +++ b/components/microprogram.py @@ -1,9 +1,6 @@ from components.ijvm import ijvm -# TODO: Switch MAR as 32bits address (multiply its value by for) -# then same for SP and LV - class Microprogram: def __init__(self,components): @@ -164,7 +161,7 @@ class Microprogram: print("-------------- RAM --------------") self.c["RAM"].dump() print("------------- Stack -------------") - self.c["RAM"].dumpRange(self.c["LV"],self.c["SP"]) + self.c["RAM"].dumpRange(self.c["LV"]*4,self.c["SP"]*4,4) # Convert address to 32bits value print("----------- Registers -----------") for key,value in self.c.items(): if key!="RAM": -- cgit v1.2.3