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authorLoïc Guégan <manzerbredes@mailbox.org>2025-03-24 09:33:49 +0100
committerLoïc Guégan <manzerbredes@mailbox.org>2025-03-24 09:33:49 +0100
commit7741f014456df395b655b72d9ebb848af72cc37e (patch)
tree5ddae273929780ac7c0af2a26b64ba1a382e4b05 /src/boot/boot2.S
parentd3ecfe3498d73d3ba924063bc1001cca3f333170 (diff)
Init repository
Diffstat (limited to 'src/boot/boot2.S')
-rw-r--r--src/boot/boot2.S38
1 files changed, 38 insertions, 0 deletions
diff --git a/src/boot/boot2.S b/src/boot/boot2.S
new file mode 100644
index 0000000..0b61084
--- /dev/null
+++ b/src/boot/boot2.S
@@ -0,0 +1,38 @@
+ .thumb
+
+ .section .boot2, "ax"
+
+ // Disable SSI
+ ldr r0, =SSI_SSIENR
+ ldr r1, =0
+ str r1, [r0]
+
+ // Set baud rate
+ ldr r0, =SSI_BAUDR
+ ldr r1, =4
+ str r1, [r0]
+
+ // Enter XIP
+ ldr r0, =SSI_CTRLR0
+ ldr r1, =(3 << 8) | (31 << 16)
+ str r1, [r0]
+
+ // CTRLR0
+ ldr r0, =SSI_SPI_CTRLR0
+ ldr r1, =(6 << 2) | (2 << 8) | (0x03 << 24)
+ str r1, [r0]
+
+ // Enable back SSI
+ ldr r0, =SSI_SSIENR
+ ldr r1, =1
+ str r1, [r0]
+
+ // Jump to crt0.S
+ ldr r0, =0x10000101
+ bx r0
+
+ .set SSI_BASE, 0x18000000
+ .set SSI_CTRLR0, SSI_BASE + 0x00
+ .set SSI_SSIENR, SSI_BASE + 0x08
+ .set SSI_BAUDR, SSI_BASE + 0x14
+ .set SSI_SPI_CTRLR0, SSI_BASE + 0xF4