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| author | Loïc Guégan <manzerbredes@mailbox.org> | 2025-03-24 09:33:49 +0100 |
|---|---|---|
| committer | Loïc Guégan <manzerbredes@mailbox.org> | 2025-03-24 09:33:49 +0100 |
| commit | 7741f014456df395b655b72d9ebb848af72cc37e (patch) | |
| tree | 5ddae273929780ac7c0af2a26b64ba1a382e4b05 /src/boot | |
| parent | d3ecfe3498d73d3ba924063bc1001cca3f333170 (diff) | |
Init repository
Diffstat (limited to 'src/boot')
| -rw-r--r-- | src/boot/boot2.S | 38 | ||||
| -rw-r--r-- | src/boot/crt0.S | 40 |
2 files changed, 78 insertions, 0 deletions
diff --git a/src/boot/boot2.S b/src/boot/boot2.S new file mode 100644 index 0000000..0b61084 --- /dev/null +++ b/src/boot/boot2.S @@ -0,0 +1,38 @@ + .thumb + + .section .boot2, "ax" + + // Disable SSI + ldr r0, =SSI_SSIENR + ldr r1, =0 + str r1, [r0] + + // Set baud rate + ldr r0, =SSI_BAUDR + ldr r1, =4 + str r1, [r0] + + // Enter XIP + ldr r0, =SSI_CTRLR0 + ldr r1, =(3 << 8) | (31 << 16) + str r1, [r0] + + // CTRLR0 + ldr r0, =SSI_SPI_CTRLR0 + ldr r1, =(6 << 2) | (2 << 8) | (0x03 << 24) + str r1, [r0] + + // Enable back SSI + ldr r0, =SSI_SSIENR + ldr r1, =1 + str r1, [r0] + + // Jump to crt0.S + ldr r0, =0x10000101 + bx r0 + + .set SSI_BASE, 0x18000000 + .set SSI_CTRLR0, SSI_BASE + 0x00 + .set SSI_SSIENR, SSI_BASE + 0x08 + .set SSI_BAUDR, SSI_BASE + 0x14 + .set SSI_SPI_CTRLR0, SSI_BASE + 0xF4 diff --git a/src/boot/crt0.S b/src/boot/crt0.S new file mode 100644 index 0000000..7935a6e --- /dev/null +++ b/src/boot/crt0.S @@ -0,0 +1,40 @@ + .section .crt0, "ax" + +// Load data segment to SRAM + ldr r0, =__data_src__ + ldr r1, =__data_dst__ + ldr r2, =__data_size__ + mov r3, #0 +data_seg_start: + cmp r2, #0 + beq data_seg_end + ldrb r3, [r0] + strb r3, [r1] + add r0, #1 + add r1, #1 + sub r2, #1 + b data_seg_start +data_seg_end: + +// Init bss in SRAM + ldr r0, =__bss_start__ + ldr r1, =__bss_size__ + mov r2, #0 +bss_init_start: + cmp r1, #0 + beq bss_init_end + strb r2, [r0] + add r0, #1 + sub r1, #1 + b bss_init_start +bss_init_end: + + // Setup stack + ldr r0, =SRAM_END + mov sp, r0 + + // Start kernel + ldr r0, =main + blx r0 + + .set SRAM_END, 0x20042000 |