diff options
Diffstat (limited to 'MicSim/components/ram.py')
| -rw-r--r-- | MicSim/components/ram.py | 18 |
1 files changed, 12 insertions, 6 deletions
diff --git a/MicSim/components/ram.py b/MicSim/components/ram.py index 6a5b02e..62edb0c 100644 --- a/MicSim/components/ram.py +++ b/MicSim/components/ram.py @@ -34,8 +34,8 @@ class Ram: """ Write data to memory based Mic-1 architecture """ - addr=self.c["MAR"]*4 # Don't forget MAR address 32bits block of memory - if addr>self.lastAddr: + addr=self.c["MAR"] + if addr>self.lastAddr or addr<0: raise ValueError("You get out of the ram by trying to set a value at address {}, max address is {}".format(addr,self.lastAddr)) #### Split bytes and write #### self.data[addr+3]=self.c["MDR"] & 0xFF @@ -48,13 +48,13 @@ class Ram: """ Read data from memory based Mic-1 architecture """ - addr=self.c["MAR"]*4 # Don't forget MAR address 32bits block of memory + addr=self.c["MAR"] value=None try: #### Combine bytes #### value=self.data[addr]<<24|(self.data[addr+1]<<16)|(self.data[addr+2]<<8)|(self.data[addr+3]) except: - if addr>self.lastAddr: + if addr>self.lastAddr or addr<0: raise ValueError("You get out of the ram by trying to get value at address {}, max address is {}".format(addr,self.lastAddr)) if(value==None): return(0) @@ -75,9 +75,15 @@ class Ram: return(0) return(value) - def dump(self): + def getData(self): """ - Fetch RAM data (usefull for unit tests) + Get RAM data (usefull for unit tests) """ return(self.data) + + def setData(self,data): + """ + Set RAM data (usefull for unit tests) + """ + self.data=data |