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from components.ijvm import ijvm
class Ram:
def __init__(self,components,size):
self.data=dict()
self.lastAddr=size-1
self.c=components
def loadRamFile(self,filepath):
"""
Load a Ram file into self.data
"""
data=dict()
addr=0
f=open(filepath,"r")
for line in f.readlines():
line=line.rstrip() # remove \n
if line in ijvm:
data[addr]=int(ijvm[line])
else:
try:
value=int(line,0)
except:
raise ValueError("Invalide RAM entry: Address {} value {}".format(addr,line))
if value>255:
raise ValueError("Ram contain values that does not fit in a byte: value {} at address {}".format(value,addr))
data[addr]=value
addr+=1
f.close()
self.data=data
def write(self):
"""
Write data to memory based Mic-1 architecture
"""
addr=self.c["MAR"]*4 # Don't forget MAR address 32bits block of memory
if addr>self.lastAddr:
raise ValueError("You get out of the ram by trying to set a value at address {}, max address is {}".format(addr,self.lastAddr))
#### Split bytes and write ####
self.data[addr+3]=self.c["MDR"] & 0xFF
self.data[addr+2]=self.c["MDR"]>>8 & 0xFF
self.data[addr+1]=self.c["MDR"]>>16 & 0xFF
self.data[addr]=self.c["MDR"]>>24 & 0xFF
def read(self):
"""
Read data from memory based Mic-1 architecture
"""
addr=self.c["MAR"]*4 # Don't forget MAR address 32bits block of memory
value=None
try:
#### Combine bytes ####
value=self.data[addr]<<24|(self.data[addr+1]<<16)|(self.data[addr+2]<<8)|(self.data[addr+3])
except:
if addr>self.lastAddr:
raise ValueError("You get out of the ram by trying to get value at address {}, max address is {}".format(addr,self.lastAddr))
if(value==None):
return(0)
return(value)
def fetch(self):
"""
Fetch next byte from memory based Mic-1 architecture
"""
addr=self.c["PC"]
value=None
try:
value=self.data[addr]
except:
if addr>self.lastAddr:
raise ValueError("You get out of the ram by trying to get value at address {}, max address is {}".format(addr,self.lastAddr))
if(value==None):
return(0)
return(value)
def dump(self):
"""
Fetch RAM data (usefull for unit tests)
"""
return(self.data)
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