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authorLoic GUEGAN <loic.guegan@yahoo.fr>2018-09-02 16:31:49 +0200
committerLoic GUEGAN <loic.guegan@yahoo.fr>2018-09-02 16:31:49 +0200
commita110465a4261e582025b6344facb7fa65c0acd56 (patch)
tree69f92f3186d47e2dc4a6b811c35238b02b0ec37d /micsim.py
parentcec2994481b3df8422603f864c1286524d5b3eff (diff)
Add unit tests, refactoring
Diffstat (limited to 'micsim.py')
-rwxr-xr-xmicsim.py15
1 files changed, 0 insertions, 15 deletions
diff --git a/micsim.py b/micsim.py
deleted file mode 100755
index 46df648..0000000
--- a/micsim.py
+++ /dev/null
@@ -1,15 +0,0 @@
-#!/usr/bin/python
-
-from components.microprogram import Microprogram
-from components.ram import Ram
-from components.caretaker import Caretaker
-
-c=Caretaker() # Init components
-RAM=Ram(c,5000) # Init ram
-RAM.loadRamFile("./ram.txt") # Load Ram from file
-c["RAM"]=RAM # Add ram to components
-
-
-mic=Microprogram(c) # Create micro program
-mic.run() # Run the micro program
-mic.dump() # Dump ram