Add unit tests, refactoring

11 files changed, 70 insertions, 48 deletions

diff --git a/components/__init__.py b/MicSim/components/__init__.py
index e69de29..e69de29 100644
--- a/components/__init__.py
+++ b/MicSim/components/__init__.py
diff --git a/components/caretaker.py b/MicSim/components/caretaker.py
index ab20fba..ab20fba 100644
--- a/components/caretaker.py
+++ b/MicSim/components/caretaker.py
diff --git a/components/ijvm.py b/MicSim/components/ijvm.py
index 86f5f63..86f5f63 100644
--- a/components/ijvm.py
+++ b/MicSim/components/ijvm.py
diff --git a/components/microprogram.py b/MicSim/components/microprogram.py
index 6147921..ec84886 100644
--- a/components/microprogram.py
+++ b/MicSim/components/microprogram.py
@@ -32,14 +32,29 @@ class Microprogram:
 		"""
 			Read data into memory
 		"""
-		data=self.c["RAM"].read()
-		self.c["MDR"]=data
+		little_endian=self.c["RAM"].read()
+		##### Build little endian version of MDR ####
+		big_endian=(little_endian&0xFF)<<24
+		big_endian=big_endian|(((little_endian>>8)&0xFF)<<16)
+		big_endian=big_endian|(((little_endian>>16)&0xFF)<<8)
+		big_endian=big_endian|((little_endian>>24)&0xFF)
+		##############################################
+		self.c["MDR"]=big_endian
 		
 	def wr(self):
 		"""
 			Write data into memory
 		"""
-		self.c["RAM"].write()
+		##### Build little endian version of MDR ####
+		little_endian=(self.c["MDR"]&0xFF)<<24
+		little_endian=little_endian|(((self.c["MDR"]>>8)&0xFF)<<16)
+		little_endian=little_endian|(((self.c["MDR"]>>16)&0xFF)<<8)
+		little_endian=little_endian|((self.c["MDR"]>>24)&0xFF)
+		##############################################
+		big_endian=self.c["MDR"] # Backup MDR before change it to little endian
+		self.c["MDR"]=little_endian # Load little endian value
+		self.c["RAM"].write() # Write little endian value into memory
+		self.c["MDR"]=big_endian # Restore big endian
 
 	def exec(self): # TODO: Implement opcode
 		"""
@@ -187,16 +202,3 @@ class Microprogram:
 		self.fetch();self.c["PC"]+=1 # Needed because memory access take 1 cycle in simulation
 		self.c["PC"]=self.c["PC"]+1
 
-	def dump(self):
-		"""
-			Print RAM, stack and registers
-		"""
-		print("-------------- RAM --------------")
-		self.c["RAM"].dump()
-		print("------------- Stack -------------")
-		self.c["RAM"].dumpRange(self.c["LV"]*4,self.c["SP"]*4,4) # Convert address to 32bits value
-		print("----------- Registers -----------")
-		for key,value in self.c.items():
-			if key!="RAM":
-				print("{}={}".format(key,value))
-		print("---------------------------------")
diff --git a/components/ram.py b/MicSim/components/ram.py
index dd99ada..6a5b02e 100644
--- a/components/ram.py
+++ b/MicSim/components/ram.py
@@ -37,11 +37,11 @@ class Ram:
 		addr=self.c["MAR"]*4 # Don't forget MAR address 32bits block of memory
 		if addr>self.lastAddr:
 			raise ValueError("You get out of the ram by trying to set a value at address {}, max address is {}".format(addr,self.lastAddr))
-		#### Little endian ####
-		self.data[addr]=self.c["MDR"] & 0xFF
-		self.data[addr+1]=self.c["MDR"] & 0xFF00
-		self.data[addr+2]=self.c["MDR"] & 0xFF0000
-		self.data[addr+3]=self.c["MDR"] & 0xFF000000
+		#### Split bytes and write ####
+		self.data[addr+3]=self.c["MDR"] & 0xFF
+		self.data[addr+2]=self.c["MDR"]>>8 & 0xFF
+		self.data[addr+1]=self.c["MDR"]>>16 & 0xFF
+		self.data[addr]=self.c["MDR"]>>24 & 0xFF
 
 	
 	def read(self):
@@ -51,8 +51,8 @@ class Ram:
 		addr=self.c["MAR"]*4 # Don't forget MAR address 32bits block of memory
 		value=None
 		try:
-			#### Little endian ####
-			value=(self.data[addr+3]<<24)|(self.data[addr+2]<<16)|(self.data[addr+1]<<8)|self.data[addr]
+			#### Combine bytes ####
+			value=self.data[addr]<<24|(self.data[addr+1]<<16)|(self.data[addr+2]<<8)|(self.data[addr+3])
 		except:
 			if addr>self.lastAddr:
 				raise ValueError("You get out of the ram by trying to get value at address {}, max address is {}".format(addr,self.lastAddr))
@@ -77,18 +77,7 @@ class Ram:
 		
 	def dump(self):
 		"""
-			Simple dump helper
+			Fetch RAM data (usefull for unit tests)
 		"""
-		for key,value in self.data.items():
-			#print("{}:{}".format(key,bin(value)[2:]))
-			print("{}:{}".format(key,value))
-		
-	def dumpRange(self,start,end,step):
-		"""
-			Another dump helper
-		"""
-		for i in range(start,end+1,step):
-			try:
-				print("{}:{}".format(i,self.data[i]))
-			except:
-				print("{}:0".format(i))
+		return(self.data)
+
diff --git a/micsim.py b/MicSim/micsim.py
index 46df648..a45311f 100755
--- a/micsim.py
+++ b/MicSim/micsim.py
@@ -12,4 +12,7 @@ c["RAM"]=RAM 					# Add ram to components
 
 mic=Microprogram(c) 			# Create micro program
 mic.run() 						# Run the micro program
-mic.dump() 						# Dump ram
+
+mic.rd()
+print(bin(c["MDR"]))
+print(RAM.dump())
diff --git a/MicSim/ram.txt b/MicSim/ram.txt
new file mode 100644
index 0000000..660c3c6
--- /dev/null
+++ b/MicSim/ram.txt
@@ -0,0 +1,2 @@
+BIPUSH
+9
diff --git a/MicSim/test/__init__.py b/MicSim/test/__init__.py
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/MicSim/test/__init__.py
diff --git a/MicSim/test/test_ram.py b/MicSim/test/test_ram.py
new file mode 100644
index 0000000..1570e0d
--- /dev/null
+++ b/MicSim/test/test_ram.py
@@ -0,0 +1,34 @@
+
+from components.ram import Ram
+import unittest
+from random import randint
+
+
+class RamTest(unittest.TestCase):
+	
+	def setUp(self):
+		"""
+			Init test
+		"""
+		self.caretaker=dict({"MDR":0,"MAR":0,"MBR":0,"PC":0})
+
+	def test_write(self):
+		"""
+			Test write method
+		"""
+		toWrite=randint(0,2**32) # Pick a random number to write
+		self.caretaker["MDR"]=toWrite
+		ram=Ram(self.caretaker,10000)
+		ram.write() # Write a random number at address 0
+		
+		data=ram.dump() # Dump ram
+		##### Test if everything is written using big endian model #####
+		self.assertEqual((toWrite>>24)&0xFF,data[self.caretaker["MAR"]])
+		self.assertEqual((toWrite>>16)&0xFF,data[self.caretaker["MAR"]+1])
+		self.assertEqual((toWrite>>8)&0xFF,data[self.caretaker["MAR"]+2])
+		self.assertEqual(toWrite&0xFF,data[self.caretaker["MAR"]+3])
+
+
+
+if __name__ == "__main__":
+	unittest.main()
diff --git a/README.md b/README.md
index 50ddb63..2fa18f1 100644
--- a/README.md
+++ b/README.md
@@ -9,7 +9,8 @@ It is simple, you have to:
  3. Enjoy !
 
 ### I want to know more about it....
-All the architecture components are located in _components_ folder:
+Source code is located in MicSim folder. All the components used for the Mic-1 architecture are 
+located in _MicSim/components_ folder:
  - **ijvm.py** Contains standard IJVM constant
  - **microprogram.py** Contains IJVM implementation that use Mic-1 architecture
  - **caretaker.py** Hold all the Mic-1 architecture components (registers, ram etc..)
diff --git a/ram.txt b/ram.txt
deleted file mode 100644
index 9cfc244..0000000
--- a/ram.txt
+++ /dev/null
@@ -1,9 +0,0 @@
-BIPUSH
--4
-IFLT
-0
-4
-BIPUSH
-6
-BIPUSH
-7