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authorLoic GUEGAN <loic.guegan@yahoo.fr>2018-09-01 23:23:19 +0200
committerLoic GUEGAN <loic.guegan@yahoo.fr>2018-09-01 23:23:19 +0200
commitcec2994481b3df8422603f864c1286524d5b3eff (patch)
tree56b1444a6ac243330a94ac774858e2159740dd7f
parent4a9d274fd70ce2531311f19debcf22f0faa1f9b2 (diff)
Add micro-instructions IFEQ and IFLT
-rw-r--r--components/microprogram.py33
-rw-r--r--ram.txt10
2 files changed, 40 insertions, 3 deletions
diff --git a/components/microprogram.py b/components/microprogram.py
index 869a2ae..6147921 100644
--- a/components/microprogram.py
+++ b/components/microprogram.py
@@ -145,6 +145,26 @@ class Microprogram:
elif opcode==ijvm["OUT"]:
self.fetch();self.c["PC"]+=1 # Fetch byte to push in MBR
print(str(chr(self.c["MBRU"])),end="") # MBRU because no char which are negative
+ elif opcode==ijvm["IFEQ"]:
+ self.c["SP"]=self.c["SP"]-1
+ self.c["MAR"]=self.c["SP"]
+ self.c["OPC"]=self.c["TOS"]
+ self.rd()
+ self.c["TOS"]=self.c["MDR"]
+ if self.c["OPC"]==0:
+ self.T()
+ else:
+ self.F()
+ elif opcode==ijvm["IFLT"]:
+ self.c["SP"]=self.c["SP"]-1
+ self.c["MAR"]=self.c["SP"]
+ self.c["OPC"]=self.c["TOS"]
+ self.rd()
+ self.c["TOS"]=self.c["MDR"]
+ if self.c["OPC"]<0:
+ self.T()
+ else:
+ self.F()
elif opcode==ijvm["HALT"]:
return(1)
else:
@@ -154,6 +174,19 @@ class Microprogram:
raise RuntimeError("Instruction {} not found on address {}".format(opcode,self.c["PC"]-1))
return(0)
+ def T(self): # This function is here just to follow ijvm implementation of "Structured Computer Organization"
+ self.fetch();self.c["PC"]+=1 # exactly like GOTO implementation
+ self.c["OPC"]=self.c["PC"]-1 # exactly like GOTO implementation
+ ###### GOTO2 #####
+ self.c["H"]=self.c["MBR"]<<8
+ self.fetch();self.c["PC"]+=1 # Fetch second byte
+ self.c["H"]=self.c["MBRU"]|self.c["H"]
+ self.c["PC"]=self.c["OPC"]+self.c["H"]
+ ##################
+ def F(self): # This function is here just to follow ijvm implementation of "Structured Computer Organization"
+ self.fetch();self.c["PC"]+=1 # Needed because memory access take 1 cycle in simulation
+ self.c["PC"]=self.c["PC"]+1
+
def dump(self):
"""
Print RAM, stack and registers
diff --git a/ram.txt b/ram.txt
index fdbf3c2..9cfc244 100644
--- a/ram.txt
+++ b/ram.txt
@@ -1,5 +1,9 @@
BIPUSH
-7
+-4
+IFLT
+0
+4
+BIPUSH
+6
BIPUSH
-8
-IADD
+7