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| author | Loic GUEGAN <loic.guegan@yahoo.fr> | 2018-09-02 18:55:31 +0200 |
|---|---|---|
| committer | Loic GUEGAN <loic.guegan@yahoo.fr> | 2018-09-02 18:55:31 +0200 |
| commit | 76d847cf01fb5ed14ccfac70f2c9684142a3cb22 (patch) | |
| tree | e2657887e21b057c9f480a1d1cf952ef5c3c0e67 /MicSim/components/ram.py | |
| parent | d0fc22d3e90e951ae6d9b0ec2ed6974a1e07a121 (diff) | |
Update RAM
Diffstat (limited to 'MicSim/components/ram.py')
| -rw-r--r-- | MicSim/components/ram.py | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/MicSim/components/ram.py b/MicSim/components/ram.py index a0f708e..fa2198d 100644 --- a/MicSim/components/ram.py +++ b/MicSim/components/ram.py @@ -37,6 +37,8 @@ class Ram: addr=self.c["MAR"] if addr>self.lastAddr or addr<0: raise ValueError("You get out of the ram by trying to set a value at address {}, max address is {}".format(addr,self.lastAddr)) + if self.c["MDR"] >=2**32: + raise ValueError("You try to write a the value {} at address {} but this value does not fit in a int".format(self.c["MDR"],addr)) #### Split bytes and write #### self.data[addr+3]=self.c["MDR"] & 0xFF self.data[addr+2]=self.c["MDR"]>>8 & 0xFF |