Update RAM

2 files changed, 8 insertions, 0 deletions

diff --git a/MicSim/components/ram.py b/MicSim/components/ram.py
index a0f708e..fa2198d 100644
--- a/MicSim/components/ram.py
+++ b/MicSim/components/ram.py
@@ -37,6 +37,8 @@ class Ram:
 		addr=self.c["MAR"]
 		if addr>self.lastAddr or addr<0:
 			raise ValueError("You get out of the ram by trying to set a value at address {}, max address is {}".format(addr,self.lastAddr))
+		if self.c["MDR"] >=2**32:
+			raise ValueError("You try to write a the value {} at address {} but this value does not fit in a int".format(self.c["MDR"],addr))
 		#### Split bytes and write ####
 		self.data[addr+3]=self.c["MDR"] & 0xFF
 		self.data[addr+2]=self.c["MDR"]>>8 & 0xFF
diff --git a/MicSim/test/test_ram.py b/MicSim/test/test_ram.py
index a60cd4f..58e42cb 100644
--- a/MicSim/test/test_ram.py
+++ b/MicSim/test/test_ram.py
@@ -43,6 +43,12 @@ class RamTest(unittest.TestCase):
 		ram=Ram(self.caretaker,1000)
 		with self.assertRaises(Exception):
 			ram.write()
+		# Try to write that cannot fit in a int
+		self.caretaker["MDR"]=2**32
+		self.caretaker["MAR"]=0
+		ram=Ram(self.caretaker,1000)
+		with self.assertRaises(Exception):
+			ram.write()
 		
 	def test_read(self):
 		"""