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| author | Loïc Guégan <manzerbredes@mailbox.org> | 2025-03-24 09:33:49 +0100 |
|---|---|---|
| committer | Loïc Guégan <manzerbredes@mailbox.org> | 2025-03-24 09:33:49 +0100 |
| commit | 7741f014456df395b655b72d9ebb848af72cc37e (patch) | |
| tree | 5ddae273929780ac7c0af2a26b64ba1a382e4b05 /src/libs/addrmap.h | |
| parent | d3ecfe3498d73d3ba924063bc1001cca3f333170 (diff) | |
Init repository
Diffstat (limited to 'src/libs/addrmap.h')
| -rw-r--r-- | src/libs/addrmap.h | 87 |
1 files changed, 87 insertions, 0 deletions
diff --git a/src/libs/addrmap.h b/src/libs/addrmap.h new file mode 100644 index 0000000..4de7b80 --- /dev/null +++ b/src/libs/addrmap.h @@ -0,0 +1,87 @@ +#ifndef __ADDRMAP__ +#define __ADDRMAP__ + +// ----- SIO ----- +#define SIO_BASE 0xd0000000 +#define SIO_CPUID SIO_BASE + 0x000 +#define SIO_GPIO_OE SIO_BASE + 0x020 +#define SIO_GPIO_OUT_XOR SIO_BASE + 0x01c +#define SIO_SPINLOCK0 SIO_BASE + 0x100 +#define SIO_SPINLOCK31 SIO_BASE + 0x17c + +// ----- RESET ----- +#define RESETS_BASE 0x4000c000 +#define RESETS_RESET RESETS_BASE + 0x0 +#define RESETS_DONE RESETS_BASE + 0x8 + +// ----- Cortex M0+ ----- +#define PPB_BASE 0xe0000000 // M0PLUS CPU registers +#define PPB_SYST_CSR PPB_BASE + 0xe010 +#define PPB_SYST_RVR PPB_BASE + 0xe014 +#define PPB_SYST_CVR PPB_BASE + 0xe018 +#define PPB_SYST_CALIB PPB_BASE + 0xe01c +#define PPB_NVIC_ISER PPB_BASE + 0xe100 +#define PPB_NVIC_ISPR PPB_BASE + 0xe200 +#define PPB_NVIC_ICPR PPB_BASE + 0xe280 +#define PPB_VTOR PPB_BASE + 0xed08 + +// ----- APB Peripherals ----- +// IO_BANK0 +#define IO_BANK0_BASE 0x40014000 +#define IO_BANK0_GPIO25_STATUS IO_BANK0_BASE + 0x0C8 +#define IO_BANK0_GPIO25_CTRL IO_BANK0_BASE + 0x0CC +// CLOCKS +#define CLOCKS_BASE 0x40008000 +#define CLOCKS_SYS_CTRL CLOCKS_BASE + 0x03c +#define CLOCKS_SYS_DIV CLOCKS_BASE + 0x040 +#define CLOCKS_SYS_SELECTED CLOCKS_BASE + 0x044 +#define CLOCKS_REF_CTRL CLOCKS_BASE + 0x030 +#define CLOCKS_PERI_CTRL CLOCKS_BASE + 0x048 +#define CLOCKS_USB_CTRL CLOCKS_BASE + 0x054 +// XOSC +#define XOSC_BASE 0x40024000 +#define XOSC_CTRL XOSC_BASE + 0x000 +#define XOSC_STATUS XOSC_BASE + 0x004 +#define XOSC_DORMANT XOSC_BASE + 0x008 +#define XOSC_STARTUP XOSC_BASE + 0x00c +#define XOSC_COUNT XOSC_BASE + 0x01c +// PLL_SYS +#define PLL_SYS_BASE 0x40028000 +#define PLL_SYS_CS PLL_SYS_BASE + 0x000 +#define PLL_SYS_PWR PLL_SYS_BASE + 0x004 +#define PLL_SYS_FBDIV_INT PLL_SYS_BASE + 0x008 +#define PLL_SYS_PRIM PLL_SYS_BASE + 0x00c +// PLL_USB +#define PLL_USB_BASE 0x4002c000 +#define PLL_USB_CS PLL_USB_BASE + 0x000 +#define PLL_USB_PWR PLL_USB_BASE + 0x004 +#define PLL_USB_FBDIV_INT PLL_USB_BASE + 0x008 +#define PLL_USB_PRIM PLL_USB_BASE + 0x00c +// SRAM +#define SRAM_BASE 0x20000000 +#define SRAM_BANK4_BASE 0x20040000 +#define SRAM_BANK5_BASE 0x20041000 +#define SRAM_END SRAM_BASE + 0x42000 +// USB Controller +#define USBCTRL_BASE 0x50100000 +#define USBCTRL_DPSRAM_BASE USBCTRL_BASE + 0x000 +#define USBCTRL_DPSRAM_SETUP_PACKET USBCTRL_DPSRAM_BASE + 0x000 +#define USBCTRL_REGS_BASE 0x50110000 +#define USBCTRL_EP0_BUFFER0 USBCTRL_DPSRAM_BASE + 0x100 +#define USBCTRL_EP0_BUFFER_CTRL_IN USBCTRL_DPSRAM_BASE + 0x080 +#define USBCTRL_EP0_BUFFER_CTRL_OUT USBCTRL_DPSRAM_BASE + 0x084 +#define USBCTRL_EP1_ENDP_CTRL_IN USBCTRL_DPSRAM_BASE + 0x08 +#define USBCTRL_EP1_BUFFER_CTRL_IN USBCTRL_DPSRAM_BASE + 0x88 +#define USBCTRL_DATA_BUFFER_START USBCTRL_DPSRAM_BASE + 0x180 +#define USBCTRL_ADDR_ENDP USBCTRL_REGS_BASE + 0x000 +#define USBCTRL_MAINCTRL USBCTRL_REGS_BASE + 0x040 +#define USBCTRL_SIE_CTRL USBCTRL_REGS_BASE + 0x04c +#define USBCTRL_SIE_STATUS USBCTRL_REGS_BASE + 0x050 +#define USBCTRL_BUFF_STATUS USBCTRL_REGS_BASE + 0x058 +#define USBCTRL_INTR USBCTRL_REGS_BASE + 0x08c +#define USBCTRL_INTE USBCTRL_REGS_BASE + 0x090 +#define USBCTRL_INTS USBCTRL_REGS_BASE + 0x098 +#define USBCTRL_MUXING USBCTRL_REGS_BASE + 0x074 +#define USBCTRL_PWR USBCTRL_REGS_BASE + 0x078 + +#endif |