blob: fb0e58946a29f0ec095105fc28c8435b56c22a4b (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
|
from components.ijvm import ijvm
class Microprogram:
def __init__(self,components):
self.c=components # Link components to microprogram
if self.c["RAM"]==None: # Check if RAM is initialize
raise RuntimeError("Microprogram initialization fail, RAM is not initialized")
def run(self):
"""
Start microprogram
"""
self.c["LV"]=(1024)# Place stack to 1024
self.c["SP"]=(1024-1) # Init SP to LV-1 (because otherwise first element of the stack will be enty because of BIPUSH impl
for i in range(1,30): # Launche first 30 insctructions
self.fetch() # Fetch
self.c["PC"]+=1 # INC PC after fetch
if self.exec()==1: # Execute opcode and halt if return code is 1
break;
def fetch(self):
"""
Fetch next byte from memory into MBR
"""
opcode=self.c["RAM"].fetch()
self.c["MBR"]=opcode # Opcode to MBR
def rd(self):
"""
Read data into memory
"""
data=self.c["RAM"].read()
self.c["MDR"]=data
def wr(self):
"""
Write data into memory
"""
self.c["RAM"].write()
def exec(self): # TODO: Implement opcode
"""
Execute next opcode
"""
opcode=self.c["MBR"] # Get loaded OpCode
if opcode==ijvm["NOP"]: # NOP
pass
elif opcode==ijvm["BIPUSH"]: # BIPUSH
self.fetch();self.c["PC"]+=1 # Fetch byte to push in MBR
self.c["SP"]+=1 # Increment stack pointer
self.c["MAR"]=self.c["SP"] # Copy SP to MAR
self.c["MDR"]=self.c["MBR"] # Set MDR to MBR
self.c["TOS"]=self.c["MBR"] # Set MDR to MBR
self.wr() # Write data to stack
elif opcode==ijvm["IADD"]:
self.c["SP"]-=1
self.c["MAR"]=self.c["SP"]
self.c["H"]=self.c["TOS"]
self.rd()
self.c["TOS"]=self.c["MDR"]+self.c["H"]
self.c["MDR"]=self.c["TOS"]
self.wr()
elif opcode==ijvm["ISUB"]:
self.c["SP"]-=1
self.c["MAR"]=self.c["SP"]
self.c["H"]=self.c["TOS"]
self.rd()
self.c["TOS"]=self.c["MDR"]-self.c["H"]
self.c["MDR"]=self.c["TOS"]
self.wr()
elif opcode==ijvm["POP"]:
self.c["SP"]-=1
self.c["MAR"]=self.c["SP"]
self.rd()
self.c["TOS"]=self.c["MDR"]
elif opcode==ijvm["DUP"]:
self.c["SP"]+=1
self.c["MAR"]=self.c["SP"]
self.c["MDR"]=self.c["TOS"]
self.wr()
elif opcode==ijvm["IAND"]:
self.c["SP"]-=1
self.c["MAR"]=self.c["SP"]
self.c["H"]=self.c["TOS"]
self.rd()
self.c["TOS"]=(self.c["MDR"] & self.c["H"])
self.c["MDR"]=self.c["TOS"]
self.wr()
elif opcode==ijvm["IOR"]:
self.c["SP"]-=1
self.c["MAR"]=self.c["SP"]
self.c["H"]=self.c["TOS"]
self.rd()
self.c["TOS"]=(self.c["MDR"] | self.c["H"])
self.c["MDR"]=self.c["TOS"]
self.wr()
elif opcode==ijvm["SWAP"]:
self.c["MAR"]=self.c["SP"]-1
self.rd()
self.c["MAR"]=self.c["SP"]
self.c["H"]=self.c["MDR"]
self.wr()
self.c["MDR"]=self.c["TOS"]
self.c["MAR"]=self.c["SP"]-1
self.wr()
self.c["TOS"]=self.c["H"]
elif opcode==ijvm["ILOAD"]:
self.fetch();self.c["PC"]+=1 # Fetch local variable to push onto the stack
self.c["H"]=self.c["LV"]
self.c["MAR"]=self.c["MBRU"]+self.c["H"]
self.rd()
self.c["SP"]+=1
self.c["MAR"]=self.c["SP"]
self.wr()
self.c["TOS"]=self.c["MDR"]
elif opcode==ijvm["ISTORE"]:
self.fetch();self.c["PC"]+=1 # Fetch local variable offset where to store
self.c["H"]=self.c["LV"]
self.c["MAR"]=self.c["MBRU"]+self.c["H"]
self.c["MDR"]=self.c["TOS"]
self.wr()
self.c["SP"]-=1
self.c["MAR"]=self.c["SP"]
self.rd()
self.c["TOS"]=self.c["MDR"]
elif opcode==ijvm["IINC"]:
self.fetch();self.c["PC"]+=1 # Fetch local variable offset to inc
self.c["H"]=self.c["LV"]
self.c["MAR"]=self.c["MBRU"]+self.c["H"]
self.rd()
self.fetch();self.c["PC"]+=1 # Fetch inc value
self.c["H"]=self.c["MDR"]
self.c["MDR"]=self.c["MBR"]+self.c["H"]
self.wr()
elif opcode==ijvm["OUT"]:
self.fetch();self.c["PC"]+=1 # Fetch byte to push in MBR
print(str(chr(self.c["MBR"])),end="")
elif opcode==ijvm["HALT"]:
return(1)
else:
if opcode in ijvm:
print("Instruction {} not yet implemented.".format(ijvm[opcode]))
else:
raise RuntimeError("Instruction {} not found".format(opcode))
return(0)
def dump(self):
"""
Print RAM, stack and registers
"""
print("-------------- RAM --------------")
self.c["RAM"].dump()
print("------------- Stack -------------")
self.c["RAM"].dumpRange(self.c["LV"],self.c["SP"])
print("----------- Registers -----------")
for key,value in self.c.items():
if key!="RAM":
print("{}={}".format(key,value))
print("---------------------------------")
|
