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from components.ijvm import ijvm
class Microprogram:
def __init__(self,components):
self.c=components # Link components to microprogram
if self.c["RAM"]==None: # Check if RAM is initialize
raise RuntimeError("Microprogram initialization fail, RAM is not initialized")
def run(self):
"""
Start microprogram
"""
self.c["LV"]=(1024)# Place stack to 1024
self.c["SP"]=(1024-1) # Init SP to LV-1 (because otherwise first element of the stack will be enty because of BIPUSH impl
for i in range(1,30): # Launche first 30 insctructions
self.fetch() # Fetch
self.c["PC"]+=1 # INC PC after fetch
if self.exec()==1: # Execute opcode and halt if return code is 1
break;
def fetch(self):
"""
Fetch next byte from memory into MBR
"""
opcode=self.c["RAM"].fetch()
self.c["MBR"]=opcode # Opcode to MBR
def rd(self):
"""
Read data into memory
"""
data=self.c["RAM"].read()
self.c["MDR"]=data
def wr(self):
"""
Write data into memory
"""
self.c["RAM"].write()
def exec(self):# link: https://users-cs.au.dk/bouvin/dComArk/2015/noter/Note_2/#Instructions
"""
Execute next opcode
"""
opcode=self.c["MBR"] # Get loaded OpCode
if opcode==ijvm["NOP"]: # NOP
pass
elif opcode==ijvm["BIPUSH"]: # BIPUSH
self.fetch();self.c["PC"]+=1 # Fetch byte to push in MBR
self.c["SP"]+=1 # Increment stack pointer
self.c["MAR"]=self.c["SP"] # Copy SP to MAR
self.c["MDR"]=self.c["MBR"] # Set MDR to MBR
self.c["TOS"]=self.c["MBR"] # Set MDR to MBR
self.wr() # Write data to stack
elif opcode==ijvm["IADD"]:
self.c["SP"]-=1
self.c["MAR"]=self.c["SP"]
self.c["H"]=self.c["TOS"]
self.rd()
self.c["TOS"]=self.c["MDR"]+self.c["H"]
self.c["MDR"]=self.c["TOS"]
self.wr()
elif opcode==ijvm["ISUB"]:
self.c["SP"]-=1
self.c["MAR"]=self.c["SP"]
self.c["H"]=self.c["TOS"]
self.rd()
self.c["TOS"]=self.c["MDR"]-self.c["H"]
self.c["MDR"]=self.c["TOS"]
self.wr()
elif opcode==ijvm["POP"]:
self.c["SP"]-=1
self.c["MAR"]=self.c["SP"]
self.rd()
self.c["TOS"]=self.c["MDR"]
elif opcode==ijvm["DUP"]:
self.c["SP"]+=1
self.c["MAR"]=self.c["SP"]
self.c["MDR"]=self.c["TOS"]
self.wr()
elif opcode==ijvm["IAND"]:
self.c["SP"]-=1
self.c["MAR"]=self.c["SP"]
self.c["H"]=self.c["TOS"]
self.rd()
self.c["TOS"]=(self.c["MDR"] and self.c["H"])
self.c["MDR"]=self.c["TOS"]
self.wr()
elif opcode==ijvm["IOR"]:
self.c["SP"]-=1
self.c["MAR"]=self.c["SP"]
self.c["H"]=self.c["TOS"]
self.rd()
self.c["TOS"]=(self.c["MDR"] or self.c["H"])
self.c["MDR"]=self.c["TOS"]
self.wr()
elif opcode==ijvm["SWAP"]:
self.c["MAR"]=self.c["SP"]-1
self.rd()
self.c["MAR"]=self.c["SP"]
self.c["H"]=self.c["MDR"]
self.wr()
self.c["MDR"]=self.c["TOS"]
self.c["MAR"]=self.c["SP"]-1
self.wr()
self.c["TOS"]=self.c["H"]
elif opcode==ijvm["OUT"]:
self.fetch();self.c["PC"]+=1 # Fetch byte to push in MBR
print(str(chr(self.c["MBR"])),end="")
elif opcode==ijvm["HALT"]:
return(1)
else:
if opcode in ijvm:
print("Instruction {} not yet implemented.".format(ijvm[opcode]))
else:
raise RuntimeError("Instruction {} not found".format(opcode))
return(0)
def dump(self):
"""
Print RAM, stack and registers
"""
print("-------------- RAM --------------")
self.c["RAM"].dump()
print("------------- Stack -------------")
self.c["RAM"].dumpRange(self.c["LV"],self.c["SP"])
print("----------- Registers -----------")
for key,value in self.c.items():
if key!="RAM":
print("{}={}".format(key,value))
print("---------------------------------")
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