diff options
Diffstat (limited to 'MicSim/components/microprogram.py')
| -rw-r--r-- | MicSim/components/microprogram.py | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/MicSim/components/microprogram.py b/MicSim/components/microprogram.py index c2a3552..12f38e4 100644 --- a/MicSim/components/microprogram.py +++ b/MicSim/components/microprogram.py @@ -8,13 +8,14 @@ class Microprogram: if self.c["RAM"]==None: # Check if RAM is initialize raise RuntimeError("Microprogram initialization fail, RAM is not initialized") - def run(self): + def run(self,constantPoolLocation, stackLocation): """ Start microprogram """ - self.c["LV"]=(1024)# Place stack to 1024 - self.c["SP"]=(1024-1) # Init SP to LV-1 (because otherwise first element of the stack will be enty because of BIPUSH impl - + self.c["LV"]=stackLocation# Place stack to 1024 + self.c["SP"]=stackLocation-1 # Init SP to LV-1 (because otherwise first element of the stack will be enty because of BIPUSH impl + self.c["CPP"]=constantPoolLocation + for i in range(1,30): # Launche first 30 insctructions self.fetch() # Fetch self.c["PC"]+=1 # INC PC after fetch @@ -202,6 +203,7 @@ class Microprogram: self.c["H"]=self.c["MBRU"]|self.c["H"] self.c["PC"]=self.c["OPC"]+self.c["H"] ################## + def F(self): # This function is here just to follow ijvm implementation of "Structured Computer Organization" self.fetch();self.c["PC"]+=1 # Needed because memory access take 1 cycle in simulation self.c["PC"]=self.c["PC"]+1 |