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authorLoic GUEGAN <loic.guegan@yahoo.fr>2018-08-31 18:42:12 +0200
committerLoic GUEGAN <loic.guegan@yahoo.fr>2018-08-31 18:42:12 +0200
commit27268a12532a3f332bb06ff71c947e15755734c8 (patch)
tree59e44879f685423eeebf6710e7673650a2c7de6c /micsim.py
parenta31c5667846b291056f29d3ef7bdf0f4bf175e10 (diff)
Add source code
Diffstat (limited to 'micsim.py')
-rwxr-xr-xmicsim.py17
1 files changed, 17 insertions, 0 deletions
diff --git a/micsim.py b/micsim.py
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+#!/usr/bin/python
+
+from components.microprogram import Microprogram
+from components.ram import Ram
+from components.caretaker import Caretaker
+
+c=Caretaker() # Init components
+RAM=Ram(c,5000) # Init ram
+RAM.loadRamFile("./ram.txt") # Load Ram from file
+c["RAM"]=RAM # Add ram to components
+
+
+mic=Microprogram(c) # Create micro program
+mic.run() # Run the micro program
+mic.dump() # Dump ram
+
+