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| author | Loic GUEGAN <loic.guegan@yahoo.fr> | 2018-08-31 18:42:12 +0200 |
|---|---|---|
| committer | Loic GUEGAN <loic.guegan@yahoo.fr> | 2018-08-31 18:42:12 +0200 |
| commit | 27268a12532a3f332bb06ff71c947e15755734c8 (patch) | |
| tree | 59e44879f685423eeebf6710e7673650a2c7de6c /micsim.py | |
| parent | a31c5667846b291056f29d3ef7bdf0f4bf175e10 (diff) | |
Add source code
Diffstat (limited to 'micsim.py')
| -rwxr-xr-x | micsim.py | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/micsim.py b/micsim.py new file mode 100755 index 0000000..1e4db48 --- /dev/null +++ b/micsim.py @@ -0,0 +1,17 @@ +#!/usr/bin/python + +from components.microprogram import Microprogram +from components.ram import Ram +from components.caretaker import Caretaker + +c=Caretaker() # Init components +RAM=Ram(c,5000) # Init ram +RAM.loadRamFile("./ram.txt") # Load Ram from file +c["RAM"]=RAM # Add ram to components + + +mic=Microprogram(c) # Create micro program +mic.run() # Run the micro program +mic.dump() # Dump ram + + |
