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| author | Loic GUEGAN <loic.guegan@yahoo.fr> | 2018-09-01 17:22:49 +0200 |
|---|---|---|
| committer | Loic GUEGAN <loic.guegan@yahoo.fr> | 2018-09-01 17:22:49 +0200 |
| commit | 94377da94d085948557b25a73ce143d51611aa7f (patch) | |
| tree | 3b85312548535adb6bd70be2a56bbf5e4ff6c233 /components/ram.py | |
| parent | d58349763a312add267dbcaf53d0b9602b177d33 (diff) | |
Debug
Diffstat (limited to 'components/ram.py')
| -rw-r--r-- | components/ram.py | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/components/ram.py b/components/ram.py index ddf48d1..b6258e3 100644 --- a/components/ram.py +++ b/components/ram.py @@ -19,7 +19,13 @@ class Ram: if line in ijvm: data[addr]=int(ijvm[line]) else: - data[addr]=int(line,0) + try: + value=int(line,0) + except: + raise ValueError("Invalide RAM entry: Address {} value {}".format(addr,line)) + if value>255: + raise ValueError("Ram contain values that does not fit in a byte: value {} at address {}".format(value,addr)) + data[addr]=value addr+=1 f.close() self.data=data |
