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| author | Loic GUEGAN <loic.guegan@yahoo.fr> | 2018-09-02 21:39:51 +0200 |
|---|---|---|
| committer | Loic GUEGAN <loic.guegan@yahoo.fr> | 2018-09-02 21:39:51 +0200 |
| commit | fbd6725e84fe27d1bc764efbec2142f710855b03 (patch) | |
| tree | f78da4999d9223d6987d59daa76c13cb2dedced5 /MicSim/test/test_ram.py | |
| parent | ef427a9944e805103ed8c82d3944918b3d46d53f (diff) | |
Add test
Diffstat (limited to 'MicSim/test/test_ram.py')
| -rw-r--r-- | MicSim/test/test_ram.py | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/MicSim/test/test_ram.py b/MicSim/test/test_ram.py index 58e42cb..6baf158 100644 --- a/MicSim/test/test_ram.py +++ b/MicSim/test/test_ram.py @@ -97,8 +97,5 @@ class RamTest(unittest.TestCase): self.caretaker["PC"]=-1*randint(0,self.ramSize-1) ram.fetch() - - - if __name__ == "__main__": unittest.main() |