Debug tests

1 files changed, 19 insertions, 18 deletions

diff --git a/MicSim/test/test_ram.py b/MicSim/test/test_ram.py
index 6baf158..f755753 100644
--- a/MicSim/test/test_ram.py
+++ b/MicSim/test/test_ram.py
@@ -72,30 +72,31 @@ class RamTest(unittest.TestCase):
 			self.caretaker["MAR"]=self.ramSize
 			ram.read()
 		with self.assertRaises(Exception):
-			self.caretaker["MAR"]=-1*randint(0,self.ramSize-1)
+			self.caretaker["MAR"]=-1*randint(1,self.ramSize-1)
 			ram.read()
 			
 	def test_fetch(self):
 		"""
 			Test fetch method
 		"""
-		# Test classical fetch
-		ram=Ram(self.caretaker,self.ramSize)
-		data=dict()
-		toWrite=randint(0,256-1)
-		for i in range(0,self.ramSize):
-			data[i]=toWrite
-		ram.setData(data)
-		for i in range(0,self.ramSize):
-			self.caretaker["PC"]=i
-			self.assertEqual(toWrite,ram.fetch())
-		# Test fetch outside of memory
-		with self.assertRaises(Exception):
-			self.caretaker["PC"]=self.ramSize
-			ram.fetch()
-		with self.assertRaises(Exception):
-			self.caretaker["PC"]=-1*randint(0,self.ramSize-1)
-			ram.fetch()
+		for q in range(0,1999):
+			# Test classical fetch
+			ram=Ram(self.caretaker,self.ramSize)
+			data=dict()
+			toWrite=randint(0,256-1)
+			for i in range(0,self.ramSize):
+				data[i]=toWrite
+			ram.setData(data)
+			for i in range(0,self.ramSize):
+				self.caretaker["PC"]=i
+				self.assertEqual(toWrite,ram.fetch())
+			# Test fetch outside of memory
+			with self.assertRaises(Exception):
+				self.caretaker["PC"]=self.ramSize
+				ram.fetch()
+			with self.assertRaises(Exception):
+				self.caretaker["PC"]=-1*randint(1,self.ramSize-1)
+				ram.fetch()
 		
 if __name__ == "__main__":
 	unittest.main()