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| author | Loic GUEGAN <loic.guegan@yahoo.fr> | 2018-09-02 18:46:31 +0200 |
|---|---|---|
| committer | Loic GUEGAN <loic.guegan@yahoo.fr> | 2018-09-02 18:46:31 +0200 |
| commit | d0fc22d3e90e951ae6d9b0ec2ed6974a1e07a121 (patch) | |
| tree | cf2671b4b488cdd577f588048ea85dd9c9a0c9a3 /MicSim/components | |
| parent | 1cc7b41a1166fb16d5cd4d93df5ffb898766477a (diff) | |
Debug test on ram
Diffstat (limited to 'MicSim/components')
| -rw-r--r-- | MicSim/components/ram.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/MicSim/components/ram.py b/MicSim/components/ram.py index 62edb0c..a0f708e 100644 --- a/MicSim/components/ram.py +++ b/MicSim/components/ram.py @@ -69,7 +69,7 @@ class Ram: try: value=self.data[addr] except: - if addr>self.lastAddr: + if addr>self.lastAddr or addr<0: raise ValueError("You get out of the ram by trying to get value at address {}, max address is {}".format(addr,self.lastAddr)) if(value==None): return(0) |