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| author | Loic GUEGAN <loic.guegan@yahoo.fr> | 2018-09-02 20:02:27 +0200 |
|---|---|---|
| committer | Loic GUEGAN <loic.guegan@yahoo.fr> | 2018-09-02 20:02:27 +0200 |
| commit | ef427a9944e805103ed8c82d3944918b3d46d53f (patch) | |
| tree | 5e5f42443127d4b87011857e3d8895e025fd9b4a /MicSim/components/ram.py | |
| parent | 19ab0b8eb760457ce7a7573230d5f441cd51359d (diff) | |
Clean code
Diffstat (limited to 'MicSim/components/ram.py')
| -rw-r--r-- | MicSim/components/ram.py | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/MicSim/components/ram.py b/MicSim/components/ram.py index 59de862..2d0628e 100644 --- a/MicSim/components/ram.py +++ b/MicSim/components/ram.py @@ -11,13 +11,13 @@ class Ram: """ Load a Ram file into self.data """ - data=dict() - addr=0 + self.data=dict() f=open(filepath,"r") + addr=0 for line in f.readlines(): line=line.rstrip() # remove \n if line in ijvm: - data[addr]=int(ijvm[line]) + self.data[addr]=int(ijvm[line]) else: try: value=int(line,0) @@ -25,11 +25,10 @@ class Ram: raise ValueError("Invalide RAM entry: Address {} value {}".format(addr,line)) if value>255: raise ValueError("Ram contain values that does not fit in a byte: value {} at address {}".format(value,addr)) - data[addr]=value + self.data[addr]=value addr+=1 f.close() - self.data=data - + def write(self): """ Write data to memory based Mic-1 architecture |
