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| author | Loic GUEGAN <loic.guegan@yahoo.fr> | 2018-09-02 20:02:27 +0200 |
|---|---|---|
| committer | Loic GUEGAN <loic.guegan@yahoo.fr> | 2018-09-02 20:02:27 +0200 |
| commit | ef427a9944e805103ed8c82d3944918b3d46d53f (patch) | |
| tree | 5e5f42443127d4b87011857e3d8895e025fd9b4a /MicSim/components/caretaker.py | |
| parent | 19ab0b8eb760457ce7a7573230d5f441cd51359d (diff) | |
Clean code
Diffstat (limited to 'MicSim/components/caretaker.py')
| -rw-r--r-- | MicSim/components/caretaker.py | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/MicSim/components/caretaker.py b/MicSim/components/caretaker.py index ab20fba..6153350 100644 --- a/MicSim/components/caretaker.py +++ b/MicSim/components/caretaker.py @@ -1,13 +1,15 @@ #!/usr/bin/python +from components.ram import Ram + class Caretaker: - def __init__(self): + def __init__(self,ramSize): self.objects=dict() # Create empty objects pool # Add registers to pool for reg in ["MAR","MDR", "PC", "MBR", "SP","LV","CPP","TOS","OPC","H"]: self.objects[reg]=0 - self.objects["RAM"]=None + self.objects["RAM"]=Ram(self,ramSize) def __getitem__(self,key): if key=="MBRU": # If we ask for unsigned |