src/core/apic.cc


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#include "apic.hpp"

#include "paging.hpp"
#include "types.hpp"
#include "asm.hpp"
#include "libs/stdio.hpp"

extern u64* kpml4;
char enable=0;
#define APIC_LAPIC_ADDR 0xFEE00000
#define APIC_IOAPIC_ADDR 0xFEC00000
#define APIC_LAPIC_REG_SPURIOUS 0xF0

void apic_enable(){
    // Allocate APIC registers
    paging_allocate_addr(kpml4, APIC_LAPIC_ADDR, APIC_LAPIC_ADDR, 
    PAGING_OPT_RW|PAGING_OPT_P|PAGING_OPT_PCD);
    paging_allocate_addr(kpml4, APIC_IOAPIC_ADDR, APIC_IOAPIC_ADDR, 
    PAGING_OPT_RW|PAGING_OPT_P|PAGING_OPT_PCD);

    // Configure APIC register location
    u32 h=APIC_LAPIC_ADDR>>32;
    u32 l=(APIC_LAPIC_ADDR&0xFFFFFFFF);
    l|=0x800; // Enable apic
    WRITE_MSR(0x1B,h,l);
    
    // Enable apic 2
    u8 *c_base=(u8*)APIC_LAPIC_ADDR;
    c_base+=APIC_LAPIC_REG_SPURIOUS;
    u32* base=(u32*)c_base;
    *base=0x100|(*base);

    u8 *c_base2=(u8*)APIC_IOAPIC_ADDR;
    u32* base2=(u32*)c_base2;
    *base2=0x12;
    base2=(u32*)(c_base2+0x10);
    *base2=(0x0<<12)|0x3C;
    enable=1;
}

extern "C" void ack(){
    if(enable){
        u8 data;
    do {
        inb(0x64,data);
    }
    while((data&0x01) == 0);
    inb(0x60,data);

    u8 *c_base=(u8*)(APIC_LAPIC_ADDR|0xB0);
    u32* base=(u32*)c_base;
    *base=*base|0;
    }
}