Making kernel Higher-Half

4 files changed, 127 insertions, 25 deletions

diff --git a/src/boot/boot.S b/src/boot/boot.S
index 7f12eed..73ee637 100644
--- a/src/boot/boot.S
+++ b/src/boot/boot.S
@@ -2,9 +2,7 @@
 .globl MB_INFO
 .extern _bss_start
 .extern _bss_end
-.extern boucane
-
-.set STACK_LOCATION, 0x1FFFFF
+.extern higherhalf
 
 .section .multiboot
 
@@ -37,7 +35,7 @@ mb_header_start:
 # ----------- End tag
 # ----------- Ask framebuffer tag
 .align 8
-.short 5
+.short 6
 .short 1
 .int 20
 .int 0
@@ -57,16 +55,6 @@ MB_INFO: # Will contains the Multiboot2 information data structure address
 
 _start:
 mov %ebx, (MB_INFO)
-# Zeroing the .bss section
-mov $_bss_start, %eax
-mov $_bss_end, %ebx
-start_zeroing:
-    movb $0x0, (%eax)
-    cmp %eax, %ebx
-    je end_zeroing
-    inc %eax
-    jmp start_zeroing
-end_zeroing:
 # ----- Setup PAE Paging (identity on the first 10MB)
 mov $8192, %ecx # 8*4096/4 (8 tables of 4096 byte each divide by 4 because of movl)
 mov $0, %eax
@@ -117,7 +105,7 @@ mov %eax, %cr0
 
 # Now we are in Compatibility mode
 # Now we need to set CS.L=1 (setting up a 64 bit GDT)
-lgdt (gdtr)
+lgdt (boot_gdtr)
 ljmp $0x08, $new_cs
 new_cs:
 
@@ -132,27 +120,42 @@ mov %ax, %es
 mov %ax, %fs
 mov %ax, %gs
 mov %ax, %ss
-mov $STACK_LOCATION, %esp
+mov $__stack_pma, %esp
+
+# Setup 
+call trampoline
+mov $__kernel_vma, %rsp
+
+# Zeroing the .bss section
+mov $__bss_start, %rax
+mov $__bss_end, %rbx
+start_zeroing:
+    movb $0x0, (%rax)
+    cmp %rax, %rbx
+    je end_zeroing
+    inc %rax
+    jmp start_zeroing
+end_zeroing:
 
-# Run boucane
-jmp boucane
+# Launch kernel
+call boucane
 
 # GDT
-gdt64:
-    gdt64_null:
+boot_gdt64:
+    boot_gdt64_null:
     .long 0
     .long 0
-    gdt64_cs:
+    boot_gdt64_cs:
     .long 0
     .byte 0
     .byte 0b10011100
     .byte 0b00100000
     .byte 0
-    gdt64_ds:
+    boot_gdt64_ds:
     .long 0
     .byte 0
     .byte 0b10010010
     .word 0
-gdtr:
-    .word . - gdt64 - 1
-    .quad gdt64
+boot_gdtr:
+    .word . - boot_gdt64 - 1
+    .quad boot_gdt64
diff --git a/src/boot/multiboot2.cc b/src/boot/multiboot2.cc
index d1a912d..532012e 100644
--- a/src/boot/multiboot2.cc
+++ b/src/boot/multiboot2.cc
@@ -1,9 +1,13 @@
 #include "multiboot2.hpp"
+#include "core/paging.hpp"
 #include "libs/string.hpp"
 #include "libs/stdio.hpp"
 
 u32* mb2_find_tag(u32 *mb2_info_addr, char type){
+    PAGING_MAP(mb2_info_addr);
     u32 size=(u32)mb2_info_addr[0];
+    for(u64 i=0;i<size/8;i++)
+        PAGING_MAP(mb2_info_addr+i*4096);
 
     char *location=((char*)mb2_info_addr)+8; // Goto first tag
     char *start=(char*)mb2_info_addr;
diff --git a/src/boot/multiboot2.hpp b/src/boot/multiboot2.hpp
index cc28109..db946a7 100644
--- a/src/boot/multiboot2.hpp
+++ b/src/boot/multiboot2.hpp
@@ -1,6 +1,7 @@
 #pragma once
 
 #include "core/types.hpp"
+#include "include/boucane.hpp"
 
 typedef struct TAG_HEADER {
     u32 type;
diff --git a/src/boot/trampoline.cc b/src/boot/trampoline.cc
new file mode 100644
index 0000000..b03bd43
--- /dev/null
+++ b/src/boot/trampoline.cc
@@ -0,0 +1,94 @@
+/**
+ * The usage of data that could goes
+ * to the .bss section is forbidden here
+ */
+
+#include "core/types.hpp"
+#include "core/paging.hpp"
+
+
+/// @brief Define where first PAE paging paging will be
+u64 trampoline_next_page;
+
+u64 trampoline_paging_allocate_table(){
+    for(u64 i=0;i<512;i++)
+        ((u64*)trampoline_next_page)[i]=0;
+    u64 ret=trampoline_next_page;
+    trampoline_next_page+=4096;
+    return ret;
+}
+
+
+void trampoline_paging_allocate_addr(u64* pml4_table, u64 virt, u64 phy, u16 options){
+    u64 pml4=virt>>39&0x1FF;
+    u64 pdp=virt>>30&0x1FF;
+    u64 pd=virt>>21&0x1FF;
+    u64 pt=virt>>12&0x1FF;
+    options&=0xFFF; // Ensure options are on 12bits
+    
+
+    // Solve pdp
+    if(pml4_table[pml4] == 0){
+        pml4_table[pml4]=(u64)trampoline_paging_allocate_table();
+        pml4_table[pml4]|=options;
+        trampoline_paging_allocate_addr(pml4_table,virt,phy,options);
+        return;
+    }
+
+    // Solve pd
+    u64* pdp_table=(u64*)PAGE(pml4_table[pml4]);
+    if(pdp_table[pdp] == 0){
+        pdp_table[pdp]=(u64)trampoline_paging_allocate_table();
+        pdp_table[pdp]|=options;
+        trampoline_paging_allocate_addr(pml4_table,virt,phy,options);
+        return;
+    }
+    // Solve pt
+    u64* pd_table=(u64*)PAGE(pdp_table[pdp]);
+    if(pd_table[pd] == 0){
+        pd_table[pd]=(u64)trampoline_paging_allocate_table();
+        pd_table[pd]|=options;
+        trampoline_paging_allocate_addr(pml4_table,virt,phy,options);
+        return;
+    }
+    // Solve address
+    u64* pt_table=(u64*)PAGE(pd_table[pd]);
+    if(pt_table[pt] == 0){
+        pt_table[pt]=PAGE(phy);
+        pt_table[pt]|=options;
+        return;
+    }
+}
+
+/**
+ * Setup High-Half Kernel Paging
+ */
+extern "C" void trampoline(){
+    u64 kernel_vma,stack_pma;
+    asm("movq $__kernel_vma, %0":"=r"(kernel_vma));
+    asm("movq $__userspace_pma, %0":"=r"(trampoline_next_page));
+    asm("movq $__stack_pma, %0":"=r"(stack_pma));
+
+    // ----- Build the trampoline paging tables
+    u64 *pml4=(u64*)trampoline_paging_allocate_table();
+    // Higher Half kernel
+    for(u64 i=0;i<=0x1000000;i+=4096){
+        trampoline_paging_allocate_addr(pml4,kernel_vma+i,i,0x3);
+    }
+    // Stack
+    trampoline_paging_allocate_addr(pml4,kernel_vma-4096,stack_pma,0x3);
+    // First bytes for current eip
+    for(u64 i=0;i<=0x1000000;i+=4096){
+        trampoline_paging_allocate_addr(pml4,i,i,0x3);
+    }
+    // Test
+    for(u64 i=0xe0000000;i<=0xef000000;i+=4096){
+        trampoline_paging_allocate_addr(pml4,i,i,0x3);
+    }
+
+    // Load new pml4
+    asm volatile(
+        "movq %0, %%rax        \n\t"
+        "movq %%rax, %%cr3     \n\t"
+        :: "r" (pml4));
+}
\ No newline at end of file