From 27268a12532a3f332bb06ff71c947e15755734c8 Mon Sep 17 00:00:00 2001
From: Loic GUEGAN <loic.guegan@yahoo.fr>
Date: Fri, 31 Aug 2018 18:42:12 +0200
Subject: Add source code

---
 components/microprogram.py | 103 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 103 insertions(+)
 create mode 100644 components/microprogram.py

(limited to 'components/microprogram.py')

diff --git a/components/microprogram.py b/components/microprogram.py
new file mode 100644
index 0000000..f415fcf
--- /dev/null
+++ b/components/microprogram.py
@@ -0,0 +1,103 @@
+
+from components.ijvm import ijvm
+
+class Microprogram:
+	
+	def __init__(self,components):
+		self.c=components
+		if self.c["RAM"]==None:
+			raise RuntimeError("Microprogram initialization fail, RAM is not initialized")
+	
+	def run(self):
+		self.c["LV"]=(1024)# Place stack to 1024
+		self.c["SP"]=(1024-1) # Init SP to LV-1 (because otherwise first element of the stack will be enty because of BIPUSH impl
+		
+		for i in range(1,30): # Launche first 30 insctructions
+			self.fetch() # Fetch
+			self.c["PC"]+=1 # INC PC
+			self.exec() # Execute opcode
+			
+	def fetch(self):
+		opcode=self.c["RAM"].fetch()
+		self.c["MBR"]=opcode # Opcode to MBR
+		
+	def rd(self):
+		data=self.c["RAM"].read()
+		self.c["MDR"]=data
+		
+	def wr(self):
+		self.c["RAM"].write()
+
+	def exec(self):# link: https://users-cs.au.dk/bouvin/dComArk/2015/noter/Note_2/#Instructions
+		opcode=self.c["MBR"] # Get loaded OpCode
+		if opcode==ijvm["NOP"]: # NOP
+			pass
+		elif opcode==ijvm["BIPUSH"]: # BIPUSH
+			self.fetch();self.c["PC"]+=1 # Fetch byte to push in MBR
+			self.c["SP"]+=1 # Increment stack pointer
+			self.c["MAR"]=self.c["SP"] # Copy SP to MAR
+			self.c["MDR"]=self.c["MBR"] # Set MDR to MBR
+			self.c["TOS"]=self.c["MBR"] # Set MDR to MBR
+			self.wr() # Write data to stack
+		elif opcode==ijvm["IADD"]:
+			self.c["SP"]-=1
+			self.c["MAR"]=self.c["SP"]
+			self.c["H"]=self.c["TOS"]
+			self.rd()
+			self.c["TOS"]=self.c["MDR"]+self.c["H"]
+			self.c["MDR"]=self.c["TOS"]
+			self.wr()
+		elif opcode==ijvm["ISUB"]:
+			self.c["SP"]-=1
+			self.c["MAR"]=self.c["SP"]
+			self.c["H"]=self.c["TOS"]
+			self.rd()
+			self.c["TOS"]=self.c["MDR"]-self.c["H"]
+			self.c["MDR"]=self.c["TOS"]
+			self.wr()
+		elif opcode==ijvm["POP"]:
+			self.c["SP"]-=1
+			self.c["MAR"]=self.c["SP"]
+			self.rd()
+			self.c["TOS"]=self.c["MDR"]
+		elif opcode==ijvm["DUP"]:
+			self.c["SP"]+=1
+			self.c["MAR"]=self.c["SP"]
+			self.c["MDR"]=self.c["TOS"]
+			self.wr()
+		elif opcode==ijvm["IAND"]:
+			self.c["SP"]-=1
+			self.c["MAR"]=self.c["SP"]
+			self.c["H"]=self.c["TOS"]
+			self.rd()
+			self.c["TOS"]=(self.c["MDR"] and self.c["H"])
+			self.c["MDR"]=self.c["TOS"]
+			self.wr()
+		elif opcode==ijvm["IOR"]:
+			self.c["SP"]-=1
+			self.c["MAR"]=self.c["SP"]
+			self.c["H"]=self.c["TOS"]
+			self.rd()
+			self.c["TOS"]=(self.c["MDR"] or self.c["H"])
+			self.c["MDR"]=self.c["TOS"]
+			self.wr()
+		elif opcode==ijvm["SWAP"]:
+			self.c["MAR"]=self.c["SP"]-1
+			self.rd()
+			self.c["MAR"]=self.c["SP"]
+			self.c["H"]=self.c["MDR"]
+			self.wr()
+			self.c["MDR"]=self.c["TOS"]
+			self.c["MAR"]=self.c["SP"]-1
+			self.wr()
+			self.c["TOS"]=self.c["H"]
+		else:
+			if opcode in ijvm:
+				print("Instruction {} not yet implemented.".format(ijvm[opcode]))
+			else:
+				raise RuntimeError("Instruction {} not found".format(opcode))
+	
+	def dump(self):
+		print("---------- Stack ----------")
+		self.c["RAM"].dump(self.c["LV"],self.c["SP"])
+		print("---------------------------")
-- 
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