From a110465a4261e582025b6344facb7fa65c0acd56 Mon Sep 17 00:00:00 2001
From: Loic GUEGAN <loic.guegan@yahoo.fr>
Date: Sun, 2 Sep 2018 16:31:49 +0200
Subject: Add unit tests, refactoring

---
 MicSim/test/__init__.py |  0
 MicSim/test/test_ram.py | 34 ++++++++++++++++++++++++++++++++++
 2 files changed, 34 insertions(+)
 create mode 100644 MicSim/test/__init__.py
 create mode 100644 MicSim/test/test_ram.py

(limited to 'MicSim/test')

diff --git a/MicSim/test/__init__.py b/MicSim/test/__init__.py
new file mode 100644
index 0000000..e69de29
diff --git a/MicSim/test/test_ram.py b/MicSim/test/test_ram.py
new file mode 100644
index 0000000..1570e0d
--- /dev/null
+++ b/MicSim/test/test_ram.py
@@ -0,0 +1,34 @@
+
+from components.ram import Ram
+import unittest
+from random import randint
+
+
+class RamTest(unittest.TestCase):
+	
+	def setUp(self):
+		"""
+			Init test
+		"""
+		self.caretaker=dict({"MDR":0,"MAR":0,"MBR":0,"PC":0})
+
+	def test_write(self):
+		"""
+			Test write method
+		"""
+		toWrite=randint(0,2**32) # Pick a random number to write
+		self.caretaker["MDR"]=toWrite
+		ram=Ram(self.caretaker,10000)
+		ram.write() # Write a random number at address 0
+		
+		data=ram.dump() # Dump ram
+		##### Test if everything is written using big endian model #####
+		self.assertEqual((toWrite>>24)&0xFF,data[self.caretaker["MAR"]])
+		self.assertEqual((toWrite>>16)&0xFF,data[self.caretaker["MAR"]+1])
+		self.assertEqual((toWrite>>8)&0xFF,data[self.caretaker["MAR"]+2])
+		self.assertEqual(toWrite&0xFF,data[self.caretaker["MAR"]+3])
+
+
+
+if __name__ == "__main__":
+	unittest.main()
-- 
cgit v1.2.3