From 76d847cf01fb5ed14ccfac70f2c9684142a3cb22 Mon Sep 17 00:00:00 2001 From: Loic GUEGAN Date: Sun, 2 Sep 2018 18:55:31 +0200 Subject: Update RAM --- MicSim/test/test_ram.py | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'MicSim/test/test_ram.py') diff --git a/MicSim/test/test_ram.py b/MicSim/test/test_ram.py index a60cd4f..58e42cb 100644 --- a/MicSim/test/test_ram.py +++ b/MicSim/test/test_ram.py @@ -43,6 +43,12 @@ class RamTest(unittest.TestCase): ram=Ram(self.caretaker,1000) with self.assertRaises(Exception): ram.write() + # Try to write that cannot fit in a int + self.caretaker["MDR"]=2**32 + self.caretaker["MAR"]=0 + ram=Ram(self.caretaker,1000) + with self.assertRaises(Exception): + ram.write() def test_read(self): """ -- cgit v1.2.3