From a110465a4261e582025b6344facb7fa65c0acd56 Mon Sep 17 00:00:00 2001 From: Loic GUEGAN Date: Sun, 2 Sep 2018 16:31:49 +0200 Subject: Add unit tests, refactoring --- MicSim/micsim.py | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100755 MicSim/micsim.py (limited to 'MicSim/micsim.py') diff --git a/MicSim/micsim.py b/MicSim/micsim.py new file mode 100755 index 0000000..a45311f --- /dev/null +++ b/MicSim/micsim.py @@ -0,0 +1,18 @@ +#!/usr/bin/python + +from components.microprogram import Microprogram +from components.ram import Ram +from components.caretaker import Caretaker + +c=Caretaker() # Init components +RAM=Ram(c,5000) # Init ram +RAM.loadRamFile("./ram.txt") # Load Ram from file +c["RAM"]=RAM # Add ram to components + + +mic=Microprogram(c) # Create micro program +mic.run() # Run the micro program + +mic.rd() +print(bin(c["MDR"])) +print(RAM.dump()) -- cgit v1.2.3