| Age | Commit message (Expand) | Author |
|---|---|---|
| 2018-09-01 | Add little endianess, debug memory addressing | Loic GUEGAN |
| 2018-09-01 | Debug | Loic GUEGAN |
| 2018-09-01 | Debug MBR register | Loic GUEGAN |
| 2018-09-01 | Clean code | Loic GUEGAN |
| 2018-09-01 | Add opcodes | Loic GUEGAN |
| 2018-08-31 | Clean code | Loic GUEGAN |
| 2018-08-31 | Update readme | Loic GUEGAN |
| 2018-08-31 | Clean code and add extras instructions | Loic GUEGAN |
| 2018-08-31 | Update readme | Loic GUEGAN |
| 2018-08-31 | Update readme | Loic GUEGAN |
| 2018-08-31 | Add readme | Loic GUEGAN |
| 2018-08-31 | Add source code | Loic GUEGAN |
| 2018-08-31 | Init repo with git ignore | Loic GUEGAN |
 |
index : micsim.git | |
| Study Mic-1 architecture through simulation. |
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