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Diffstat (limited to 'MicSim/test/test_ram.py')
| -rw-r--r-- | MicSim/test/test_ram.py | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/MicSim/test/test_ram.py b/MicSim/test/test_ram.py index a60cd4f..58e42cb 100644 --- a/MicSim/test/test_ram.py +++ b/MicSim/test/test_ram.py @@ -43,6 +43,12 @@ class RamTest(unittest.TestCase): ram=Ram(self.caretaker,1000) with self.assertRaises(Exception): ram.write() + # Try to write that cannot fit in a int + self.caretaker["MDR"]=2**32 + self.caretaker["MAR"]=0 + ram=Ram(self.caretaker,1000) + with self.assertRaises(Exception): + ram.write() def test_read(self): """ |