From 6bf4be8b8f3863c65f47d37c0be182971f9360bc Mon Sep 17 00:00:00 2001 From: Loic Guegan Date: Thu, 23 Jun 2022 14:06:26 +0200 Subject: Improve simulator robustness --- tests/simple_read_clock_2n/out | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'tests/simple_read_clock_2n') diff --git a/tests/simple_read_clock_2n/out b/tests/simple_read_clock_2n/out index 4fa7877..c3cb2b9 100644 --- a/tests/simple_read_clock_2n/out +++ b/tests/simple_read_clock_2n/out @@ -1,5 +1,5 @@ -[t=0.000,src=n0] Clock is 0s -[t=0.000,src=n1] Clock is 0s +[t=0.000,src=n0] Clock is 0.0s +[t=0.000,src=n1] Clock is 0.0s [t=5698.126,src=n0] Clock is 5698.1256s [t=5698.126,src=n0] Clock is 5698.1256s [t=5698.126,src=n1] Clock is 5698.1256s -- cgit v1.2.3