From fb69c7b05894cee2b8bb691ead948798a0674059 Mon Sep 17 00:00:00 2001
From: Loic Guegan <manzerbredes@mailbox.org>
Date: Fri, 30 Apr 2021 10:43:44 +0200
Subject: Setup TSS segment

---
 src/core/paging.cc | 15 ++++++++++-----
 1 file changed, 10 insertions(+), 5 deletions(-)

(limited to 'src/core/paging.cc')

diff --git a/src/core/paging.cc b/src/core/paging.cc
index b12fb4c..bad776f 100644
--- a/src/core/paging.cc
+++ b/src/core/paging.cc
@@ -1,4 +1,5 @@
 #include "paging.hpp"
+#include "core/asm.hpp"
 #include "core/types.hpp"
 #include "libs/stdio.hpp"
 #include "libs/string.hpp"
@@ -47,10 +48,7 @@ void paging_enable() {
     
     // Load new pml4
     u64 kpage_phy=((u64)kpages[0]-kvar_kernel_vma);
-    asm volatile(
-        "mov %0, %%rax        \n\t"
-        "mov %%rax, %%cr3     \n\t"
-        :: "r" (kpage_phy));
+    lpml4(kpage_phy);
 }
 
 u64* paging_allocate_contiguous(int npages){
@@ -187,6 +185,13 @@ void paging_allocate_addr(u64* pml4_table, u64 virt, u64 phy, u16 options, char
 
 u64* paging_create_task(int npages){
     u64 *pml4=PAGE_ALLOCATE();
-   // paging_allocate_addr(pml4, 0, (u64)PAGE_ALLOCATE(), PAGING_OPT_P|PAGING_OPT_RW, 0);
+
+    for(int i=0;i<npages;i++)
+        paging_allocate_addr(pml4, 0, (u64)PAGE_ALLOCATE(), PAGING_OPT_P|PAGING_OPT_RW, 0);
+
+    // Enable kernel access
+    u16 pml4_entry=kvar_kernel_vma>>39&0x1FF;
+    pml4[pml4_entry]=kpages[0][pml4_entry];
+
     return pml4;
 }
\ No newline at end of file
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