From 7db6db5ae64e7ab2626bbd898c63f58e053dc1a6 Mon Sep 17 00:00:00 2001
From: Loic Guegan <manzerbredes@mailbox.org>
Date: Sun, 25 Apr 2021 12:41:24 +0200
Subject: Debug multiboot, enable apic and ACPI table parsing

---
 src/core/apic.cc | 54 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 54 insertions(+)
 create mode 100644 src/core/apic.cc

(limited to 'src/core/apic.cc')

diff --git a/src/core/apic.cc b/src/core/apic.cc
new file mode 100644
index 0000000..a93e54e
--- /dev/null
+++ b/src/core/apic.cc
@@ -0,0 +1,54 @@
+#include "apic.hpp"
+
+#include "paging.hpp"
+#include "types.hpp"
+#include "asm.hpp"
+#include "libs/stdio.hpp"
+
+extern u64* kpml4;
+char enable=0;
+#define APIC_LAPIC_ADDR 0xFEE00000
+#define APIC_IOAPIC_ADDR 0xFEC00000
+#define APIC_LAPIC_REG_SPURIOUS 0xF0
+
+void apic_enable(){
+    // Allocate APIC registers
+    paging_allocate_addr(kpml4, APIC_LAPIC_ADDR, APIC_LAPIC_ADDR, 
+    PAGING_OPT_RW|PAGING_OPT_P|PAGING_OPT_PCD);
+    paging_allocate_addr(kpml4, APIC_IOAPIC_ADDR, APIC_IOAPIC_ADDR, 
+    PAGING_OPT_RW|PAGING_OPT_P|PAGING_OPT_PCD);
+
+    // Configure APIC register location
+    u32 h=APIC_LAPIC_ADDR>>32;
+    u32 l=(APIC_LAPIC_ADDR&0xFFFFFFFF);
+    l|=0x800; // Enable apic
+    WRITE_MSR(0x1B,h,l);
+    
+    // Enable apic 2
+    u8 *c_base=(u8*)APIC_LAPIC_ADDR;
+    c_base+=APIC_LAPIC_REG_SPURIOUS;
+    u32* base=(u32*)c_base;
+    *base=0x100|(*base);
+
+    u8 *c_base2=(u8*)APIC_IOAPIC_ADDR;
+    u32* base2=(u32*)c_base2;
+    *base2=0x12;
+    base2=(u32*)(c_base2+0x10);
+    *base2=(0x0<<12)|0x3C;
+    enable=1;
+}
+
+extern "C" void ack(){
+    if(enable){
+        u8 data;
+    do {
+        inb(0x64,data);
+    }
+    while((data&0x01) == 0);
+    inb(0x60,data);
+
+    u8 *c_base=(u8*)(APIC_LAPIC_ADDR|0xB0);
+    u32* base=(u32*)c_base;
+    *base=*base|0;
+    }
+}
\ No newline at end of file
-- 
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